sched_barrier in core::arch::amdgpu - Rust
Description: Prevent movement of some instruction types.

## sched_barrier

# Function sched_barrier

Source

    pub unsafe fn sched_barrier<const MASK: u32>()

🔬This is a nightly-only experimental API. (`stdarch_amdgpu` #149988)
Available on `target_arch=amdgpu` only.
Expand description

Prevent movement of some instruction types.

Controls the types of instructions that may be allowed to cross the intrinsic during instruction scheduling. The parameter is a mask for the instruction types that can cross the intrinsic.

- 0x0000: No instructions may be scheduled across `sched_barrier`.
- 0x0001: All, non-memory, non-side-effect producing instructions may be scheduled across `sched_barrier`, i.e. allow ALU instructions to pass.
- 0x0002: VALU instructions may be scheduled across `sched_barrier`.
- 0x0004: SALU instructions may be scheduled across `sched_barrier`.
- 0x0008: MFMA/WMMA instructions may be scheduled across `sched_barrier`.
- 0x0010: All VMEM instructions may be scheduled across `sched_barrier`.
- 0x0020: VMEM read instructions may be scheduled across `sched_barrier`.
- 0x0040: VMEM write instructions may be scheduled across `sched_barrier`.
- 0x0080: All DS instructions may be scheduled across `sched_barrier`.
- 0x0100: All DS read instructions may be scheduled across `sched_barrier`.
- 0x0200: All DS write instructions may be scheduled across `sched_barrier`.
- 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across `sched_barrier`.