core::arch::riscv32 - Rust
Description: Platform-specific intrinsics for the `riscv32` platform.

Skip to main content

## Module riscv32

Source
🔬This is a nightly-only experimental API. (`riscv_ext_intrinsics` #114544)
Available on RISC-V RV32 only.
Expand description

Platform-specific intrinsics for the `riscv32` platform.

See the module documentation for more details.

## Functions§

add8ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 8-bit signed numbers, discarding overflow bits
add16ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 16-bit signed numbers, discarding overflow bits
aes32dsiExperimental`zknd`
  AES final round decryption instruction for RV32.
aes32dsmiExperimental`zknd`
  AES middle round decryption instruction for RV32.
aes32esiExperimental`zkne`
  AES final round encryption instruction for RV32.
aes32esmiExperimental`zkne`
  AES middle round encryption instruction for RV32 with.
clmulExperimental(RISC-V RV32 or RISC-V RV64) and `zbkc`
  Carry-less multiply (low-part)
clmulhExperimental(RISC-V RV32 or RISC-V RV64) and `zbkc`
  Carry-less multiply (high-part)
clmulrExperimental(RISC-V RV32 or RISC-V RV64) and `zbc`
  Carry-less multiply (reversed)
clrs8ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of redundant sign bits of the packed 8-bit elements
clrs16ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of redundant sign bits of the packed 16-bit elements
clrs32ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of redundant sign bits of the packed 32-bit elements
clz8ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of leading zero bits of the packed 8-bit elements
clz16ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of leading zero bits of the packed 16-bit elements
clz32ExperimentalRISC-V RV32 or RISC-V RV64
  Count the number of leading zero bits of the packed 32-bit elements
cmpeq8ExperimentalRISC-V RV32 or RISC-V RV64
  Compare equality for packed 8-bit elements
cmpeq16ExperimentalRISC-V RV32 or RISC-V RV64
  Compare equality for packed 16-bit elements
cras16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross adds and subtracts packed 16-bit signed numbers, discarding overflow bits
crsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross subtracts and adds packed 16-bit signed numbers, discarding overflow bits
fence_i⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `FENCE.I` instruction
frrmExperimentalRISC-V RV32 or RISC-V RV64
  Reads the floating-point rounding mode register `frm`
hfence_gvma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for guest physical address and virtual machine
hfence_gvma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for all virtual machines and guest physical addresses
hfence_gvma_gaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for guest physical address
hfence_gvma_vmid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for given virtual machine
hfence_vvma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for given guest virtual address and guest address space
hfence_vvma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for all guest address spaces and guest virtual addresses
hfence_vvma_asid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for given guest address space
hfence_vvma_vaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Hypervisor memory management fence for given guest virtual address
hinval_gvma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for guest physical address and virtual machine
hinval_gvma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for all virtual machines and guest physical addresses
hinval_gvma_gaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for guest physical address
hinval_gvma_vmid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for given virtual machine
hinval_vvma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for given guest virtual address and guest address space
hinval_vvma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses
hinval_vvma_asid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for given guest address space
hinval_vvma_vaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate hypervisor translation cache for given guest virtual address
hlv_b⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Loads virtual machine memory by signed byte integer
hlv_bu⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Loads virtual machine memory by unsigned byte integer
hlv_h⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Loads virtual machine memory by signed half integer
hlv_hu⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Loads virtual machine memory by unsigned half integer
hlv_w⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Loads virtual machine memory by signed word integer
hlvx_hu⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Accesses virtual machine instruction by unsigned half integer
hlvx_wu⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Accesses virtual machine instruction by unsigned word integer
hsv_b⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Stores virtual machine memory by byte integer
hsv_h⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Stores virtual machine memory by half integer
hsv_w⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Stores virtual machine memory by word integer
kabs8ExperimentalRISC-V RV32 or RISC-V RV64
  Compute the absolute value of packed 8-bit signed integers
kabs16ExperimentalRISC-V RV32 or RISC-V RV64
  Compute the absolute value of packed 16-bit signed integers
kadd8ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 8-bit signed numbers, saturating at the numeric bounds
kadd16ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 16-bit signed numbers, saturating at the numeric bounds
kaddhExperimentalRISC-V RV32 or RISC-V RV64
  Adds signed lower 16-bit content of two registers with Q15 saturation
kcras16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross adds and subtracts packed 16-bit signed numbers, saturating at the numeric bounds
kcrsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross subtracts and adds packed 16-bit signed numbers, saturating at the numeric bounds
ksll8ExperimentalRISC-V RV32 or RISC-V RV64
  Logical left shift packed 8-bit elements, saturating at the numeric bounds
ksll16ExperimentalRISC-V RV32 or RISC-V RV64
  Logical left shift packed 16-bit elements, saturating at the numeric bounds
kslra8ExperimentalRISC-V RV32 or RISC-V RV64
  Logical saturating left then arithmetic right shift packed 8-bit elements
kslra8uExperimentalRISC-V RV32 or RISC-V RV64
  Logical saturating left then arithmetic right shift packed 8-bit elements
kslra16ExperimentalRISC-V RV32 or RISC-V RV64
  Logical saturating left then arithmetic right shift packed 16-bit elements
kslra16uExperimentalRISC-V RV32 or RISC-V RV64
  Logical saturating left then arithmetic right shift packed 16-bit elements
kstas16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight adds and subtracts packed 16-bit signed numbers, saturating at the numeric bounds
kstsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight subtracts and adds packed 16-bit signed numbers, saturating at the numeric bounds
ksub8ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 8-bit signed numbers, saturating at the numeric bounds
ksub16ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 16-bit signed numbers, saturating at the numeric bounds
ksubhExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts signed lower 16-bit content of two registers with Q15 saturation
nopExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `NOP` instruction
orc_bExperimental(RISC-V RV32 or RISC-V RV64) and `zbb`
  Bitwise OR-Combine, byte granule
pauseExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `PAUSE` instruction
pbsadExperimentalRISC-V RV32 or RISC-V RV64
  Calculate the sum of absolute difference of unsigned 8-bit data elements
pbsadaExperimentalRISC-V RV32 or RISC-V RV64
  Calculate and accumulate the sum of absolute difference of unsigned 8-bit data elements
pkbt16ExperimentalRISC-V RV32 or RISC-V RV64
  Pack two 16-bit data from bottom and top half from 32-bit chunks
pktb16ExperimentalRISC-V RV32 or RISC-V RV64
  Pack two 16-bit data from top and bottom half from 32-bit chunks
radd8ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the sum of packed 8-bit signed numbers, dropping least bits
radd16ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the sum of packed 16-bit signed numbers, dropping least bits
rcras16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross halves of adds and subtracts packed 16-bit signed numbers, dropping least bits
rcrsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross halves of subtracts and adds packed 16-bit signed numbers, dropping least bits
rstas16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight halves of adds and subtracts packed 16-bit signed numbers, dropping least bits
rstsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight halves of subtracts and adds packed 16-bit signed numbers, dropping least bits
rsub8ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the subtraction result of packed 8-bit signed numbers, dropping least bits
rsub16ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the subtraction result of packed 16-bit signed numbers, dropping least bits
scmple8ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 8-bit packed signed integers are less than or equal to the others
scmple16ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 16-bit packed signed integers are less than or equal to the others
scmplt8ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 8-bit packed signed integers are less than the others
scmplt16ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 16-bit packed signed integers are less than the others
sfence_inval_ir⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `SFENCE.INVAL.IR` instruction
sfence_vma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Supervisor memory management fence for given virtual address and address space
sfence_vma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Supervisor memory management fence for all address spaces and virtual addresses
sfence_vma_asid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Supervisor memory management fence for given address space
sfence_vma_vaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Supervisor memory management fence for given virtual address
sfence_w_inval⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `SFENCE.W.INVAL` instruction
sha256sig0Experimental(RISC-V RV32 or RISC-V RV64) and `zknh`
  Implements the Sigma0 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
sha256sig1Experimental(RISC-V RV32 or RISC-V RV64) and `zknh`
  Implements the Sigma1 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
sha256sum0Experimental(RISC-V RV32 or RISC-V RV64) and `zknh`
  Implements the Sum0 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
sha256sum1Experimental(RISC-V RV32 or RISC-V RV64) and `zknh`
  Implements the Sum1 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
sha512sig0hExperimental`zknh`
  Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sha512sig0lExperimental`zknh`
  Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sha512sig1hExperimental`zknh`
  Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sha512sig1lExperimental`zknh`
  Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sha512sum0rExperimental`zknh`
  Implements the Sum0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sha512sum1rExperimental`zknh`
  Implements the Sum1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
sinval_vma⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate supervisor translation cache for given virtual address and address space
sinval_vma_all⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate supervisor translation cache for all address spaces and virtual addresses
sinval_vma_asid⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate supervisor translation cache for given address space
sinval_vma_vaddr⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Invalidate supervisor translation cache for given virtual address
sll8ExperimentalRISC-V RV32 or RISC-V RV64
  Logical left shift packed 8-bit elements, discarding overflow bits
sll16ExperimentalRISC-V RV32 or RISC-V RV64
  Logical left shift packed 16-bit elements, discarding overflow bits
sm3p0Experimental(RISC-V RV32 or RISC-V RV64) and `zksh`
  Implements the P0 transformation function as used in the SM3 hash function [4, 30].
sm3p1Experimental(RISC-V RV32 or RISC-V RV64) and `zksh`
  Implements the P1 transformation function as used in the SM3 hash function [4, 30].
sm4edExperimental(RISC-V RV32 or RISC-V RV64) and `zksed`
  Accelerates the block encrypt/decrypt operation of the SM4 block cipher [5, 31].
sm4ksExperimental(RISC-V RV32 or RISC-V RV64) and `zksed`
  Accelerates the Key Schedule operation of the SM4 block cipher [5, 31] with `bs=0`.
smaqaExperimentalRISC-V RV32 or RISC-V RV64
  Multiply signed 8-bit elements and add 16-bit elements on results for packed 32-bit chunks
smaqasuExperimentalRISC-V RV32 or RISC-V RV64
  Multiply signed to unsigned 8-bit and add 16-bit elements on results for packed 32-bit chunks
smax8ExperimentalRISC-V RV32 or RISC-V RV64
  Get maximum values from 8-bit packed signed integers
smax16ExperimentalRISC-V RV32 or RISC-V RV64
  Get maximum values from 16-bit packed signed integers
smin8ExperimentalRISC-V RV32 or RISC-V RV64
  Get minimum values from 8-bit packed signed integers
smin16ExperimentalRISC-V RV32 or RISC-V RV64
  Get minimum values from 16-bit packed signed integers
sra8ExperimentalRISC-V RV32 or RISC-V RV64
  Arithmetic right shift packed 8-bit elements without rounding up
sra8uExperimentalRISC-V RV32 or RISC-V RV64
  Arithmetic right shift packed 8-bit elements with rounding up
sra16ExperimentalRISC-V RV32 or RISC-V RV64
  Arithmetic right shift packed 16-bit elements without rounding up
sra16uExperimentalRISC-V RV32 or RISC-V RV64
  Arithmetic right shift packed 16-bit elements with rounding up
srl8ExperimentalRISC-V RV32 or RISC-V RV64
  Logical right shift packed 8-bit elements without rounding up
srl8uExperimentalRISC-V RV32 or RISC-V RV64
  Logical right shift packed 8-bit elements with rounding up
srl16ExperimentalRISC-V RV32 or RISC-V RV64
  Logical right shift packed 16-bit elements without rounding up
srl16uExperimentalRISC-V RV32 or RISC-V RV64
  Logical right shift packed 16-bit elements with rounding up
stas16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight adds and subtracts packed 16-bit signed numbers, discarding overflow bits
stsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight subtracts and adds packed 16-bit signed numbers, discarding overflow bits
sub8ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 8-bit signed numbers, discarding overflow bits
sub16ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 16-bit signed numbers, discarding overflow bits
sunpkd810ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack first and zeroth into two 16-bit signed halfwords in each 32-bit chunk
sunpkd820ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack second and zeroth into two 16-bit signed halfwords in each 32-bit chunk
sunpkd830ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and zeroth into two 16-bit signed halfwords in each 32-bit chunk
sunpkd831ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and first into two 16-bit signed halfwords in each 32-bit chunk
sunpkd832ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and second into two 16-bit signed halfwords in each 32-bit chunk
swap8ExperimentalRISC-V RV32 or RISC-V RV64
  Swap the 8-bit bytes within each 16-bit halfword of a register.
swap16ExperimentalRISC-V RV32 or RISC-V RV64
  Swap the 16-bit halfwords within each 32-bit word of a register
ucmple8ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 8-bit packed unsigned integers are less than or equal to the others
ucmple16ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 16-bit packed unsigned integers are less than or equal to the others
ucmplt8ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 8-bit packed unsigned integers are less than the others
ucmplt16ExperimentalRISC-V RV32 or RISC-V RV64
  Compare whether 16-bit packed unsigned integers are less than the others
ukadd8ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 8-bit unsigned numbers, saturating at the numeric bounds
ukadd16ExperimentalRISC-V RV32 or RISC-V RV64
  Adds packed 16-bit unsigned numbers, saturating at the numeric bounds
ukaddhExperimentalRISC-V RV32 or RISC-V RV64
  Adds signed lower 16-bit content of two registers with U16 saturation
ukcras16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross adds and subtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
ukcrsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross subtracts and adds packed 16-bit unsigned numbers, saturating at the numeric bounds
ukstas16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight adds and subtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
ukstsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight subtracts and adds packed 16-bit unsigned numbers, saturating at the numeric bounds
uksub8ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 8-bit unsigned numbers, saturating at the numeric bounds
uksub16ExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
uksubhExperimentalRISC-V RV32 or RISC-V RV64
  Subtracts signed lower 16-bit content of two registers with U16 saturation
umaqaExperimentalRISC-V RV32 or RISC-V RV64
  Multiply unsigned 8-bit elements and add 16-bit elements on results for packed 32-bit chunks
umax8ExperimentalRISC-V RV32 or RISC-V RV64
  Get maximum values from 8-bit packed unsigned integers
umax16ExperimentalRISC-V RV32 or RISC-V RV64
  Get maximum values from 16-bit packed unsigned integers
umin8ExperimentalRISC-V RV32 or RISC-V RV64
  Get minimum values from 8-bit packed unsigned integers
umin16ExperimentalRISC-V RV32 or RISC-V RV64
  Get minimum values from 16-bit packed unsigned integers
unzipExperimental`zbkb`
  Place odd and even bits of the source word into upper/lower halves of the destination.
uradd8ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the sum of packed 8-bit unsigned numbers, dropping least bits
uradd16ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the sum of packed 16-bit unsigned numbers, dropping least bits
urcras16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross halves of adds and subtracts packed 16-bit unsigned numbers, dropping least bits
urcrsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Cross halves of subtracts and adds packed 16-bit unsigned numbers, dropping least bits
urstas16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight halves of adds and subtracts packed 16-bit unsigned numbers, dropping least bits
urstsa16ExperimentalRISC-V RV32 or RISC-V RV64
  Straight halves of subtracts and adds packed 16-bit unsigned numbers, dropping least bits
ursub8ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the subtraction result of packed 8-bit unsigned numbers, dropping least bits
ursub16ExperimentalRISC-V RV32 or RISC-V RV64
  Halves the subtraction result of packed 16-bit unsigned numbers, dropping least bits
wfi⚠ExperimentalRISC-V RV32 or RISC-V RV64
  Generates the `WFI` instruction
xperm4Experimental(RISC-V RV32 or RISC-V RV64) and `zbkx`
  Nibble-wise lookup of indicies into a vector.
xperm8Experimental(RISC-V RV32 or RISC-V RV64) and `zbkx`
  Byte-wise lookup of indicies into a vector in registers.
zipExperimental`zbkb`
  Place upper/lower halves of the source register into odd/even bits of the destination respectivley.
zunpkd810ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack first and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
zunpkd820ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack second and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
zunpkd830ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
zunpkd831ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and first into two 16-bit unsigned halfwords in each 32-bit chunk
zunpkd832ExperimentalRISC-V RV32 or RISC-V RV64
  Unpack third and second into two 16-bit unsigned halfwords in each 32-bit chunk